The present invention relates to a method for producing a semiconductor fixed value memory.
A semiconductor fixed value memory of integrated field effect transistors is disclosed in German Auslegeschrift No. 2,034,659, corresponding to U.S. Pat. No. 3,614,750 to John L. Janning. According to this patent, the transistors are arranged in rows and columns with pairs of source and drain electrodes and a contiguous gate electrode conductor pattern disposed on a substrate and covered by a dielectric coating. The gate electrode conductor pattern is interrupted at certain points in dependence on the information. This fixed value memory has the drawback that the fixed memory contents to be stored must already be known when the memory is produced since for every memory contents a specially adapted gate electrode conductor pattern must be provided. This makes it impossible to mass-produce and store such memories economically.
German Offenlegungsschrift No. 2,128,014 published December 14th, 1972, discloses another fixed value memory including field effect transistors in which parallel strips of opposite conductivity type are mede in a semiconductor material. Disposed above and perpendicular to these semiconductor strips are parallel conductor strips which are insulated from the substrate and the regions of opposite conductivity type contained therein by an electrically nonconductive layer of differing thickness. The semiconductor substrate contains locations of opposite conductivity type next to the parallel strips of opposite conductivity type so that they are always disposed below the parallel conductor strips which are perpendicular thereto. This memory has the principal drawback that the high integration density desired for reasons of space utilization, i.e. density of memory cells on a substrate, cannot be attained.
Such electrically programmable circuits have moreover the principal drawback that higher voltages or currents, respectively, are required for writing in the bit pattern than is required for operation of the memory. Therefore, the design of the circuits involves insurmountable difficulties particularly with respect to design of the decoding and read-out circuits. Moreover, during manufacture, the insulating layer employed for programming must meet high requirements regarding density and uniformity which make production yields in such processes rather questionable. It is furthermore very difficult to include in the manufacturing sequence for the circuits, in addition to the conventional two different layer thicknesses for the gate and field regions, a third substantially thinner layer (about 300 A), because such thin layers are particularly subject to "pinholes" and thus unevennesses in the breakthrough voltage. Moreover, a connection produced at such breakthrough by an oxide is a very unstable contact because the contact resistance may change over several powers of ten particularly under temperature stresses.